The SSD1963QL9 chip is an LCD display controller with the following main functions:
Display Function
• Frame Buffer: It has a built-in 1215k bytes frame buffer, supporting up to 864×480 at 24BPP display.
• Interface Support: It supports 18/24-bit RGB TFT generic interface panels and 8-bit serial RGB interface.
• Rotation and Mirroring: It has hardware rotation capabilities of 0, 90, 180, and 270 degrees, as well as hardware display mirroring.
• Image Parameter Adjustment: It enables programmable brightness, contrast, and saturation control. It also provides dynamic backlight control (DBC) via PWM signal.
MCU Connectivity
• Multi-bit Interface: It offers 8/9/16/18/24-bit MCU interfaces to receive graphics data and commands from the MCU.
• Tearing Effect Signal: It can output tearing effect signals to indicate display anomalies.
I/O Connectivity
• GPIO Pins: It is equipped with 4 GPIO pins that can be configured for miscellaneous display signals or used as general-purpose I/Os.
Clock and Power Management
• Built-in Clock Generator: It has a built-in clock generator that, together with the system clock and reset manager, provides clock signals for the entire system and divides the root clock for different modules.
• Power-saving Mode: It supports a deep sleep mode for power saving. The core supply power (VDD_PLL and VDDD) is 1.2V±0.1V, the I/O supply power (VDDIO) ranges from 1.65V to 3.6V, and the LCD interface supply power (VDD_LCD) is also from 1.65V to 3.6V.
Display Function
• Frame Buffer: It has a built-in 1215k bytes frame buffer, supporting up to 864×480 at 24BPP display.
• Interface Support: It supports 18/24-bit RGB TFT generic interface panels and 8-bit serial RGB interface.
• Rotation and Mirroring: It has hardware rotation capabilities of 0, 90, 180, and 270 degrees, as well as hardware display mirroring.
• Image Parameter Adjustment: It enables programmable brightness, contrast, and saturation control. It also provides dynamic backlight control (DBC) via PWM signal.
MCU Connectivity
• Multi-bit Interface: It offers 8/9/16/18/24-bit MCU interfaces to receive graphics data and commands from the MCU.
• Tearing Effect Signal: It can output tearing effect signals to indicate display anomalies.
I/O Connectivity
• GPIO Pins: It is equipped with 4 GPIO pins that can be configured for miscellaneous display signals or used as general-purpose I/Os.
Clock and Power Management
• Built-in Clock Generator: It has a built-in clock generator that, together with the system clock and reset manager, provides clock signals for the entire system and divides the root clock for different modules.
• Power-saving Mode: It supports a deep sleep mode for power saving. The core supply power (VDD_PLL and VDDD) is 1.2V±0.1V, the I/O supply power (VDDIO) ranges from 1.65V to 3.6V, and the LCD interface supply power (VDD_LCD) is also from 1.65V to 3.6V.
